Most prior art general purpose digital computers employ a central system organization in which main storage is connected to outlying secondary storage on one side and to the central processing unit on the other. The main storage hardware is frequently divided into hierarchical levels in which a small, fast access working storage is directly connected to the central processing unit and larger, slower access backing levels of bulk storage are successively connected to the first high speed working store level. For example, U.S. Pat. No. 3,218,611 to Kilburn, et at., assigned to the instant assignee, is directed toward a hierarchical organization with directory registers for keeping track of where particular data is stored.
The need for storage hierarchies in main storage results from the need for memory to keep pace with CPU speeds while, at the same time, providing the large physical memory size demanded by the need to handle large computational problems. However, large size and fast access speeds are incompatible goals in the design of main storage, for as memory capacity increases, a larger physical package results which causes an increase in transmission times. The hierarchical arrangement of main storage, although capable of matching speeds between the main storage and the CPU, introduces the necessity for separate storage transfer control programs which coordinate the transfer of data between the bulk storage and the working storage and between the work storage and the arithmetic processing units, in addition to the executive and arithmetic processing control programs necessary to carry out the basic arithmetic data processing task.
Another problem arises which is unique to signal processing computers having arithmetic pipelined architectures. Signal processing arithmetic operations are highly repetitive and it has been found that a sequential pipelined architecture can substantially enhance the throughput in performing such functions. For example, in U.S. Pat. No. 4,041,461 to G. L. Kratz, et al. entitled "Signal Analyzer System," assigned to the instant assignee, describes an arithmetic processor which contains a sequentially pipelined arithmetic architecture for carrying out highly repetitive signal processing operations such as beamforming, finite impulse response (FIR) filtering, and Fast Fourier Transforms (FFT). In order to control the arithmetic pipeline, an arithmetic element controller is contained in the arithmetic processor, containing its own microinstruction sequencer. This arithmetic element controller is, in turn, controlled by a separate control processor which serves as the supervisor and storage manager for the overall signal processing operation. Still a third processor controls data transfers between a bulk data storage and a working storage and between the bulk data storage and the input/output channels. Although the system described in the Kratz, et al. patent works well for carrying out a highly repetitive signal operation such as a Fast Fourier Transform over an extended computational period, the several processors require a fairly extensive changeover period to switch from one type of processing task to another. Thus, if it is desired to switch from a beamforming computational task to a finite impulse response filtering task and then to a Fast Fourier Transform computation within a relatively brief interval of time, the control architecture described in the Kratz, et al. patent will not easily permit such changeovers. The control processor must carry out its supervisory and storage management functions and communicate to the storage transfer controller and the arithmetic element controller the new task sequences and parameters necessary to carry out the new type of task desired.